1. Field of the Invention
The present invention relates generally chemical mechanical polish (CMP) planarizing methods for forming chemical mechanical polish (CMP) planarized layers within microelectronic fabrications. More particularly, the present invention relates to chemical mechanical polish (CMP) planarizing methods for forming residue free chemical mechanical polish (CMP) planarized layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ when forming patterned microelectronic conductor layers within microelectronic fabrications, such as but not limited to patterned microelectronic conductor contact layers and patterned microelectronic conductor interconnect layers within microelectronic fabrications, copper containing conductor materials. Similarly, it has also become common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications patterned microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, such as, for example and without limitation, organic polymer spin-on-polymer (SOP) low dielectric constant dielectric materials and silsesquioxane spin-on-glass (SOG) low dielectric constant dielectric materials.
Within the context of the present invention, comparatively low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant less than about 4.0, more preferably from about 2.0 to less than about 4.0, while for comparison purposes, conventional dielectric materials which may be employed within microelectronic fabrications, such conventional dielectric materials including but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, typically possess comparatively higher dielectric constants greater than about 4.0, and more typically from greater than about 4.0 to about 8.0.
Copper containing conductor materials are desirable for forming patterned microelectronic conductor layers within microelectronic fabrications since copper containing conductor materials typically possess enhanced electrical properties in comparison with other conductor materials, such as but not limited to aluminum containing conductor materials and tungsten containing conductor materials, which may alternatively be employed for forming patterned microelectronic conductor layers within microelectronic fabrications.
Similarly, low dielectric constant dielectric materials are desirable for forming patterned microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications since such low dielectric constant dielectric materials typically provide microelectronic fabrications with enhanced microelectronic fabrication speed and attenuated patterned microelectronic conductor layer cross-talk.
While copper containing conductor materials and low dielectric constant dielectric materials are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having interposed between their patterns patterned microelectronic dielectric layers within microelectronic fabrications, copper containing conductor materials in general, and more particularly in conjunction with low dielectric constant dielectric materials, are not without problems within the art of microelectronic fabrication for forming patterned microelectronic conductor layers having interposed between their patterns patterned microelectronic dielectric layers within microelectronic fabrications. In that regard, insofar as copper containing conductor materials are often difficult to pattern while employing reactive ion etch (RIE) plasma etch methods as are otherwise conventional for forming patterned microelectronic conductor layers within microelectronic fabrications, such patterned microelectronic conductor layers when formed within microelectronic fabrications of copper containing conductor materials are often formed employing damascene methods, including but not limited to dual damascene methods.
As is understood by a person skilled in the art, within a damascene method a blanket copper containing conductor layer is formed into an aperture formed within a patterned microelectronic layer, where the aperture typically comprises a via and/or trench defined within a patterned microelectronic dielectric layer, and the excess of the blanket copper containing conductor layer above the aperture is planarized while employing a chemical mechanical polish (CMP) planarizing method to form within the aperture a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layer, such as a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor stud layer and/or a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor interconnect layer within the corresponding via and/or the corresponding trench defined by the patterned microelectronic dielectric layer.
While such chemical mechanical polish (CMP) planarizing methods are thus useful for forming within microelectronic fabrications chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layers within microelectronic fabrications, such chemical mechanical polish (CMP) planarizing methods in turn are also not entirely without problems in the art of microelectronic fabrication for forming chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layers having interposed between their patterns patterned microelectronic dielectric layers, such as but not limited to patterned low dielectric constant microelectronic dielectric layers, within microelectronic fabrications. In that regard, it is also known in the art of microelectronic fabrication that a patterned copper containing microelectronic conductor layer, when formed employing a chemical mechanical polish (CMP) planarizing method, is often formed while providing a chemical mechanical polish (CMP) residue layer upon at least a portion of the microelectronic fabrication adjoining the patterned copper containing microelectronic conductor layer. Such a chemical mechanical polish (CMP) residue layer is in turn undesirable in the art of microelectronic fabrication since it often compromises the functionality or reliability of the microelectronic fabrication within which it is formed.
It is thus towards the goal of forming within the art of microelectronic fabrication microelectronic fabrications having formed therein chemical mechanical polish (CMP) planarized patterned copper containing conductor layers having interposed between their patterns patterned low dielectric constant dielectric layers, such as but not limited to chemical mechanical polish (CMP) planarized patterned copper containing conductor stud layers and chemical mechanical polish (CMP) planarized patterned copper containing conductor interconnect layers, having formed interposed between their patterns organic polymer spin-on-polymer (SOP) low dielectric constant patterned dielectric layers and silsesquioxane spin-on-glass (SOG) low dielectric constant patterned dielectric layers, absent chemical mechanical polish (CMP) residue layers formed within the microelectronic fabrication, that the present invention is most specifically directed. In a more general sense, the present invention is also directed towards forming within the art of microelectronic fabrication microelectronic fabrications having formed therein chemical mechanical polish (CMP) planarized patterned microelectronic layers absent chemical mechanical polish (CMP) residue layers formed within the microelectronic fabrications.
Various methods and materials have been disclosed in the art of microelectronic fabrication for forming microelectronic fabrications and microelectronic layers with desirable properties within the art of microelectronic fabrication.
For example, Schnegg et al., in U.S. Pat. No. 5,051,134, disclose a method for treating a silicon semiconductor substrate employed within an integrated circuit microelectronic fabrication with an aqueous hydrofluoric acid solution in a fashion such that there is attenuated an increase in particulate contamination upon the silicon semiconductor substrate when treating the silicon semiconductor substrate with the aqueous hydrofluoric acid solution. The method includes, when treating the silicon semiconductor substrate with the aqueous hydrofluoric acid solution, incorporating an additive into the aqueous hydrofluoric acid solution, where the additive is selected from the group consisting of at least one of: (1) an organic compound capable of forming an inclusion compound; and (2) an acid which in addition to not oxidizing the silicon semiconductor substrate also has a pKa of less than 3.14.
In addition, Humata, in U.S. Pat. No. 5,476,817, discloses a method for forming within a microelectronic fabrication a patterned conductor lead layer structure having formed therein a patterned conductor lead layer having formed interposed between its patterns a patterned low dielectric constant dielectric layer, where the patterned conductor lead layer structure has an attenuated susceptibility to joule heating, thus providing the microelectronic fabrication with an enhanced reliability. The method realizes the foregoing objects by employing when fabricating the patterned conductor lead layer structure within the microelectronic fabrication a thermally conductive electrical insulator material which dissipates heat from the patterned conductor lead layer within the patterned conductor lead layer structure to a dummy conductor lead layer within the pattern ed conductor lead layer structure.
Further, Sasaki et al., in U.S. Pat. No. 5,770,095, disclose a chemical mechanical polish (CMP) planarizing method and a chemical mechanical polish (CMP) slurry composition for use when forming from a blanket conductor layer within a microelectronic fabrication a chemical mechanical polish (CMP) planarized patterned conductor layer within the microelectronic fabrication, where the chemical mechanical polish (CMP) planarized patterned conductor layer is formed with attenuated dishing within the chemical mechanical polish (CMP) planarized patterned conductor layer. The chemical mechanical polish (CMP) planarizing method and the chemical mechanical polish (CMP) slurry composition realize the foregoing objects by incorporating into the chemical mechanical polish (CMP) slurry composition employed within the chemical mechanical polish (CMP) planarizing method in addition to a chemical mechanical polish (CMP) etching agent a chemical mechanical polish (CMP) protective film forming agent.
Still further, Green et al., in U.S. Pat. No. 5,814,562, disclose a method for cleaning a silicon semiconductor substrate employed within an integrated circuit microelectronic fabrication such that there may be formed incident to thermal oxidation of the silicon semiconductor substrate a thermal silicon oxide layer with enhanced electrical properties for use within the integrated circuit microelectronic fabrication. The method realizes the foregoing object by employing within the method: (1) a first treatment of the silicon semiconductor substrate with a vapor mixture of anhydrous hydrofluoric acid and methanol in a nitrogen carrier gas, followed by; (2) a second treatment of the silicon semiconductor substrate with a chlorine gas which has been irradiated with broadband ultraviolet radiation.
Finally, Ulrich et al., in U.S. Pat. No. 5,897,379, disclose a method for selectively removing from only edge portions of a substrate employed within a microelectronic fabrication portions of a blanket copper containing layer formed over the substrate employed within the microelectronic fabrication, while not oxidizing remaining portions of the blanket copper containing layer formed over non-edge portions of the substrate. The method employs a masking of selected central portions of the blanket copper containing layer formed over the substrate and a subsequent wet chemical etching of the unmasked portions of the blanket copper containing layer at the edge portions of the substrate.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications chemical mechanical polish (CMP) planarized patterned copper containing conductor layers having formed interposed between their patterns patterned low dielectric constant dielectric layers with attenuated chemical mechanical polish (CMP) planarizing residue formation within the microelectronic fabrications. More generally desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrication residue free chemical mechanical polish (CMP) planarized patterned layers within microelectronic fabrications.
It is towards the foregoing objects that the present invention is both specifically and more generally directed.
A first object of the present invention is to provide a method for forming a residue free chemical mechanical polish (CMP) planarized patterned layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the chemical mechanical polish (CMP) planarized patterned layer is a chemical mechanical polish (CMP) planarized patterned copper containing conductor layer formed into an aperture defined by a pair of patterned low dielectric constant dielectric layers within the microelectronic fabrication.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for removing from over a substrate a chemical mechanical polish (CMP) residue layer. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate: (1) a chemical mechanical polish (CMP) substrate layer having an aperture formed therein; (2) a chemical mechanical polish (CMP) planarized patterned layer formed within the aperture within the chemical mechanical polish (CMP) substrate layer; and (3) a chemical mechanical polish (CMP) residue layer formed upon at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer, where the at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer has a first aqueous contact angle. There is then treated the at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer having the first aqueous contact angle to provide at least one of a hydrophilic chemical mechanical polish (CMP) substrate layer and a hydrophilic chemical mechanical polish (CMP) planarized patterned layer having a second aqueous contact angle less than the first aqueous contact angle. Finally, there is then removed the chemical mechanical polish (CMP) residue layer from the at least one of the hydrophilic chemical mechanical polish (CMP) substrate layer and the hydrophilic chemical mechanical polish (CMP) planarized patterned layer with an aqueous cleaner composition.
There is provided by the present invention a method for forming a residue free chemical mechanical polish (CMP) planarized patterned layer within a microelectronic fabrication. The present invention realizes the foregoing object by treating at least one of a chemical mechanical polish (CMP) substrate layer and a chemical mechanical polish (CMP) planarized patterned layer, at least either having formed thereupon a chemical mechanical polish (CMP) residue layer, to form at least one of a corresponding hydrophilic chemical mechanical polish (CMP) substrate layer and a corresponding hydrophilic chemical mechanical polish (CMP) planarized patterned layer, at least either having formed thereupon the chemical mechanical polish (CMP) residue layer, prior to removing therefrom with an aqueous cleaner composition the chemical mechanical polish (CMP) residue layer.
The present invention may be employed where the chemical mechanical polish (CMP) planarized patterned layer is a chemical mechanical polish (CMP) planarized patterned copper containing conductor layer formed into an aperture defined by a pair of low dielectric constant patterned dielectric layers which comprise a chemical mechanical polish (CMP) substrate layer within the microelectronic fabrication. The present invention does not discriminate with respect to the nature of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer provided that at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer: (1) has formed thereupon a chemical mechanical polish (CMP) residue layer; and (2) is also susceptible to being treated such that there is formed at least one of a corresponding hydrophilic chemical mechanical polish (CMP) substrate layer and a corresponding hydrophilic chemical mechanical polish (CMP) planarized patterned layer having a second aqueous contact angle less than a first aqueous contact angle of at least one of the corresponding chemical mechanical polish (CMP) substrate layer and the corresponding chemical mechanical polish (CMP) planarized patterned layer.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials which although reasonably accessible and generally available within fields not necessarily related to the present invention may nonetheless be readily adapted to provide the present invention. Since it is thus a process control, materials selection and materials application which provides at least in part the present invention, rather than exclusively the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.